military and industrial temperature ranges idt54/74fct543t/at/ct/dt fast cmos octal latched transceiver 1 june 2002 military and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. ? 2002 integrated device technology, inc. dsc-5489/2 features: ? std., a, c, and d grades ? low input and output leakage 1a (max.) ? cmos power levels ? true ttl input and output compatibility: ?v oh = 3.3v (typ.) ?v ol = 0.3v (typ.) ? high drive outputs (-15ma i oh , 64ma i ol ) ? meets or exceeds jedec standard 18 specifications ? military product compliant to mil-std-883, class b and desc listed (dual marked) ? power off disable outputs permit "live insertion" ? available in the following packages: ? industrial: soic, ssop, qsop ? military: cerdip, lcc functional block diagram idt54/74fct543t/at/ct/dt fast cmos octal latched transceiver description: the fct543t is a non-inverting octal transceiver built using an advanced dual metal cmos technology. this device contains two sets of eight d-type latches with separate input and output controls for each set. for data flow from a to b, for example, the a-to-b enable ( ceab ) input must be low in order to enter data from a 0 ?a 7 or to take data from b 0 ?b 7 , as indicated in the function table. with ceab low, a low signal on the a-to-b latch enable ( leab ) input makes the a-to-b latches transparent; a subsequent low-to- high transition of the leab signal puts the a latches in the storage mode and their outputs no longer change with the a inputs. with ceab and oeab both low, the 3-state b output buffers are active and reflect the data present at the output of the a latches. control of data from b to a is similar, but uses the ceba , leba and oeba inputs. a 1 q oeba a 2 a 3 a 4 a 5 a 6 a 7 b 1 b 2 b 3 b 4 b 5 b 6 b 7 ceba leba oeab ceab leab detail a x 7 d le q d le detail a a 0 b 0
military and industrial temperature ranges 2 idt54/74fct543t/at/ct/dt fast cmos octal latched transceiver pin configuration symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed vcc by +0.5v unless otherwise noted. 2. inputs and vcc terminals only. 3. output and i/o terminals only. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. cerdip/ soic/ ssop/ qsop top view 2 3 1 20 19 18 15 16 9 10 a 6 a 7 b 6 b 7 23 22 24 21 17 5 6 7 4 8 a 1 oeba a 0 v cc a 2 a 5 a 3 a 4 ceba b 2 b 0 b 1 b 3 b 4 b 5 leba 13 14 11 12 ceab gnd leab oeab 1 2 3 4 5 7 8 6 9 10 11 12 13 14 15 16 17 18 19 20 index a 1 21 22 23 24 25 26 27 28 a 2 a 3 a 4 a 5 a 6 a 7 nc g n d n c nc n c b 1 b 2 b 3 b 4 b 5 b 7 l e a b o e a b b 6 a 0 o e b a l e b a v c c c e b a b 0 c e a b pin description pin names description oeab a-to-b output enable input (active low) oeba b-to-a output enable input (active low) ceab a-to-b enable input (active low) ceba b-to-a enable input (active low) leab a-to-b latch enable input (active low) leba b-to-a latch enable input (active low) a 0 ?a 7 a-to-b data inputs or b-to-a 3-state outputs b 0 ?b 7 b-to-a data inputs or a-to-b 3-state outputs lcc top view
military and industrial temperature ranges idt54/74fct543t/at/ct/dt fast cmos octal latched transceiver 3 notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. the test limit for this parameter is 5a at t a = ?55c. 5. this parameter is guaranteed but not tested. symbol parameter test conditions (1) min. typ. (2) max. unit v oh output high voltage v cc = min i oh = ?6ma mil 2.4 3.3 ? v in = v ih or v il i oh = ?8ma ind v i oh = ?12ma mil 2 3 ? i oh = ?15ma ind v ol output low voltage v cc = min i ol = 48ma mil ? 0.3 0.55 v v in = v ih or v il i ol = 64ma ind i os short circuit current v cc = max., v o = gnd (3) ?60 ?120 ?225 ma i off input/output power off leakage (5) v cc = 0v, v in or v o 4.5v ? ? 1a output drive characteristics symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (4) v cc = max. v i = 2.7v ? ? 1a i il input low current (4) v cc = max. v i = 0.5v ? ? 1a i ozh high impedance output current v cc = max v o = 2.7v ? ? 1a i ozl (3-state output pins) (4) v o = 0.5v ? ? 1 i i input high current (4) v cc = max., v i = v cc (max.) ? ? 1a v ik clamp diode voltage v cc = min, i in = -18ma ? ?0.7 ?1.2 v v h input hysteresis ? ? 200 ? mv i cc quiescent power supply current v cc = max., v in = gnd or v cc ? 0.01 1 ma dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 5.0v 5%; military: t a = ?55c to +125c, v cc = 5.0v 10% function table (1, 2) for a-to-b (symmetric with b-to-a) latch output inputs status buffers ceab leab oeab a-to-b b 0 ?b 7 h x x storing high z x h x storing x x x h x high z l l l transparent current a inputs l h l storing previous* a inputs notes: 1. * before leab low-to-high transition h = high voltage level l = low voltage level x = don?t care 2. a-to-b data flow shown; b-to-a flow control is the same, except using ceba , leba and oeba .
military and industrial temperature ranges 4 idt54/74fct543t/at/ct/dt fast cmos octal latched transceiver symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply current v cc = max. ? 0.5 2 ma ttl inputs high v in = 3.4v (3) i ccd dynamic power supply v cc = max., outputs open v in = v cc ? 0.15 0.25 ma/ current (4) ceab and oeab = gnd v in = gnd mhz ceba = v cc one input toggling 50% duty cycle i c total power supply current (6) v cc = max., outputs open v in = v cc ? 1.5 3.5 ma f cp = 10mhz ( leab )v in = gnd 50% duty cycle ceab and oeab = gnd ceba = v cc v in = 3.4v ? 2 5.5 one bit toggling v in = gnd at fi = 5mhz 50% duty cycle v cc = max., outputs open v in = v cc ? 3.8 7.3 (5) ma f cp = 10mhz ( leab )v in = gnd 50% duty cycle ceab and oeab = gnd ceba = v cc v in = 3.4v ? 6 16.3 (5) eight bits toggling v in = gnd at fi = 2.5mhz 50% duty cycle notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input; (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of ? i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f cp /2+ f i n i ) i cc = quiescent current ? i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = output frequency n i = number of outputs at f i all currents are in milliamps and all frequencies are in megahertz. power supply characteristics
military and industrial temperature ranges idt54/74fct543t/at/ct/dt fast cmos octal latched transceiver 5 notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this limit is guaranteed but not tested. switching characteristics over operating range - industrial 74fct543at 74fct543ct 74fct543dt symbol parameter condition (1) min . (2) max. min . (2) max. min . (2) max. unit t plh propagation delay c l = 50pf 1.5 6.5 1.5 5.3 1.5 4.4 ns t phl transparant mode r l = 500 ? ax to bx or bx to ax t plh propagation delay 1.5 8 1.5 7 1.5 5 ns t phl leba to ax, leab to bx t pzh output enable time 1.5 9 1.5 8 1.5 5.4 ns t pzl oeba or oeab to ax or bx ceba or ceab to ax or bx t phz output disable time 1.5 7.5 1.5 6.5 1.5 4.3 ns t plz oeba or oeab to ax or bx ceba or ceab to ax or bx t su set-up time, high or low 2 ? 2 ? 1.5 ? ns ax or bx to leba or leab t h hold time, high or low 2 ? 2 ? 1.5 ? ns ax or bx to leba or leab t w leba or leab pulse width low 5 ? 5 ? 3 (3) ?ns switching characteristics over operating range - military 54fct543t 54fct543at 54fct543ct symbol parameter condition (1) min . (2) max. min . (2) max. min . (2) max. unit t plh propagation delay c l = 50pf 1.5 10 1.5 7.5 1.5 6.1 ns t phl transparant mode r l = 500 ? ax to bx or bx to ax t plh propagation delay 1.5 14 1.5 9 1.5 8 ns t phl leba to ax, leab to bx t pzh output enable time 1.5 14 1.5 10 1.5 9 ns t pzl oeba or oeab to ax or bx ceba or ceab to ax or bx t phz output disable time 1.5 13 1.5 8.5 1.5 7.5 ns t plz oeba or oeab to ax or bx ceba or ceab to ax or bx t su set-up time, high or low 3 ? 2 ? 2 ? ns ax or bx to leba or leab t h hold time, high or low 2 ? 2 ? 2 ? ns ax or bx to leba or leab t w leba or leab pulse width low 5 ? 5 ? 5 ? ns
military and industrial temperature ranges 6 idt54/74fct543t/at/ct/dt fast cmos octal latched transceiver pulse generator r t d.u.t . v cc v in c l v out 50pf 500 ? 500 ? 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
military and industrial temperature ranges idt54/74fct543t/at/ct/dt fast cmos octal latched transceiver 7 ordering information idt xx temp. range fct xxxx device type xx package x process fast cmos octal latched transceiver 543t 543at 543ct 543dt so py q industrial options small outline ic shrink small outline package quarter-size small outline package d l military options cerdip leadless chip carrier blank b industrial mil-std-883, class b 54 74 ? 55 c to +125 c ? 40 c to +85 c corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com 6/24/2002 updated as per pdns logic-00-07 and logic-01-04 data sheet document history
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